The maximum frequency of the unconstrained designs is recorded. When the achieved frequency calculated by the post-route timing analysis is no better than the previous run, the iterations stop and the best results are recorded. For each iteration of the Xilinx tool chain, the goal frequency is set to 3% faster than the last achieved frequency. The Xilinx place and route tool set is next started with an initially low frequency goal placed in the “1-clock only UCF” file. This was done so we can establish the maximum frequency for each clock on the design separately. Each clock sweep produces a unique netlist in which the other clocks are not optimized. On designs with multiple clocks, each clock was swept higher independently while the others were held at an initial low value.
The best EDIF file is passed forward to the Xilinx tool set. The outputs from the Synplify_pro iterations are the EDIF design netlist and the translated constraints file in NCF format. When the resulting performance falls backward or fails to improve, the best results are preserved. The first synthesis is with a relaxed clock requirement of 15MHz and the resulting clock frequency estimate is used to set a clock-frequency goal 5% faster than that result. The frequency iteration script invokes the Synplify_pro tool in batch mode, examines the timing report, increments the target frequency by writing a “1-clock only SDC file” which contains a “define_clock” constraint with the target frequency value, then runs the tool again. A frequency sweeping script for logic synthesis is used to achieve the best EDIF netlist for moving forward into place and route. The operating frequency estimates are recorded for constrained and unconstrained cases after synthesis and after place and route. Run Xilinx ngdbuild, map, and par to create a routed netlist and post-route timing report.Īdditional scripting is added to the flow to evaluate the impact of Focus generated timing exceptions on maximum clock frequency. Default settings were used for logic synthesis, with the exception of the “auto-constrain frequency” option which was turned off.ģ. Synthesize the RTL with Synplify_pro to create an EDIF file and an NCF constraint file containing the constraints translated to match the EDIF netlist and in Xilinx compatible format. Run Focus to generate timing exceptions.Ģ. Two cases were run for each design clock: the unconstrained case where there were no timing exceptions, and the constrained case where in addition to the clock, Focus generated timing exceptions were included. The Xilinx tool set of ngdbuild, map and par, read the EDIF netlist and constraint file from Synplify_pro, and create a routed design, final timing reports and a device programming file.įigure 1 shows the flow from RTL synthesis through place and route. Synplify_pro also prepares a translated constraint file to feed forward the same timing requirements to place and route. This set of constraints is used in initial logic synthesis and affects the resulting EDIF file generated for Xilinx place and route tools. Synplify_pro is a full-featured logic synthesis tool which reads constraints for false paths and multi-cycle paths as well as IO and clock constraints. Focus also provides the ability to verify the generated timing exceptions through assertions that can be checked as part of functional simulation. Focus generates false and multi-cycle paths in industry standard constraint formats. In about one quarter of these designs, the timing exceptions can make a one-speed grade improvement in FPGA performance after place and route.įishTail’s Focus is designed to identify the timing exceptions in the design, and requires data that is normally already available for your design synthesizable RTL, clock definitions and boundary constraints. We compare the design’s maximum clock frequency before and after place and route, with and without timing exceptions. In this paper we have studied the impact of timing exceptions on nine designs using Synplify_pro from Synplicity for logic synthesis, Xilinx tools for place and route, and Focus from FishTail to generate false and multi-cycle path timing exceptions. These timing exceptions have the ability to improve FPGA QoR by relaxing constraints on the timing paths of the design and potentially allow the FPGA to run faster. FishTail’s Focus tool can generate false path and multi-cycle path timing exceptions for the FPGA designer before the first synthesis run. FPGA designers are typically working with prototype designs without much synthesis history, so on the first pass of the design they will not have developed a set of false path and multi-cycle path constraints.
0 kommentar(er)
